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K6T8008C2M Family
Document Title
1Mx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 1.0 Initial draft Finalize - Adopt New Code system. - Improve VIN, VOUT max. on ABSOLUTE MAXIMUM RATINGS'from ' 7.0V to VCC+0.5V. - Change Icc: from 12 to 10mA - Change Icc1: from 10 to 12mA
Draft Date
June 22, 1999 February 29, 2000
Remark
Advance Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 1.00 February 2000
K6T8008C2M Family
1Mx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
* Process Technology: TFT * Organization: 1M x8 * Power Supply Voltage: 4.5~5.5V * Low Data Retention Voltage: 2.0V(Min) * Three state output and TTL Compatible * Package Type: 44-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6T8008C2M families are fabricated by SAMSUNGs advanced CMOS process technology. The families support industrial operating temperature ranges for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family K6T8008C2M-B K6T8008C2M-F Operating Temperature Commercial(0~70C) Industrial(-40~85C) Vcc Range Speed Standby (ISB1, Max) 50A 80A Operating (ICC2, Max) 70mA PKG Type
4.5~5.5V
55 1)/70ns
44-TSOP2-400F/R
1. The parameter is measured with 50pF test load.
PIN DESCRIPTION
A4 A3 A2 A1 A0 CS1 NC NC I/O1 I/O2 Vcc Vss I/O3 I/O4 NC NC WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE CS2 A8 NC NC I/O8 I/O7 Vss Vcc I/O6 I/O5 NC NC A9 A10 A11 A12 A13 A14 A5 A6 A7 OE CS2 A8 NC NC I/O8 I/O7 Vss Vcc I/O6 I/O5 NC NC A9 A10 A11 A12 A13 A14 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A4 A3 A2 A1 A0 CS1 NC NC I/O1 I/O2 Vcc Vss I/O3 I/O4 NC NC WE A19 A18 A17 A16 A15
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
Vcc Vss Row Addresses
Row select
Memory array 1024 rows 1024x8 columns
44-TSOP2 Forward
44-TSOP2 Reverse
I/O1~I/O8
Data cont
I/O Circuit Column select
Data cont Column Addresses
Name CS1, CS2 OE WE I/O1~I/O8
Function Chip Select Inputs Output Enable Input Write Enable Input Data Inputs/Outputs
Name Vcc Vss
Function Power Ground
CS1 CS2 OE WE
A0~A19 Address Inputs NC No Connect
Control Logic
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2
Revision 1.00 February 2000
K6T8008C2M Family
PRODUCT LIST
Commercial Temperature Products(0~70C) Part Name K6T8008C2M-TB55 K6T8008C2M-TB70 K6T8008C2M-RB55 K6T8008C2M-RB70 Function 44-TSOP2-F, 55ns, 5.0V, LL 44-TSOP2-F, 70ns, 5.0V, LL 44-TSOP2-R, 55ns, 5.0V, LL 44-TSOP2-R, 70ns, 5.0V, LL
CMOS SRAM
Industrial Temperature Products(-40~85C) Part Name K6T8008C2M-TF55 K6T8008C2M-TF70 K6T8008C2M-RF55 K6T8008C2M-RF70 Function 44-TSOP2-F, 55ns, 5.0V, LL 44-TSOP2-F, 70ns, 5.0V, LL 44-TSOP2-R, 55ns, 5.0V, LL 44-TSOP2-R, 70ns, 5.0V, LL
FUNCTIONAL DESCRIPTION
CS1 H X L L L CS2 X L H H H OE X X H L X WE X X H H L I/O1~8 High-Z High-Z High-Z Dout Din Mode Deselected Deselected Output Disabled Read Write Power Standby Standby Active Active Active
Note: X means dont care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Ratings -0.5 to VCC+0.5V -0.3 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 Unit V V W C C C Remark K6T8008C2M-B K6T8008C2M-F
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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K6T8008C2M Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Product K6T8008C2M Family All Family K6T8008C2M Family K6T8008C2M Family Min 4.5 0 2.2 -0.5
3)
CMOS SRAM
Typ 5.0 0 Max 5.5 0 Vcc+0.5 0.8
2)
Unit V V V V
Note: 1. Commercial Product: TA=0 to 70C, otherwise specified. Industrial Product: TA=-40 to 85C, otherwise specified. 2. Overshoot: VCC+3.0V in case of pulse width 30ns. 3. Undershoot: -3.0V in case of pulse width 30ns. 4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE 1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ILI ILO ICC ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) VOL VOH ISB ISB1 VIN=Vss to Vcc CS1=VIH, CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS1=VIL, CS2=VIH, WE=VIH, VIN=VIH or VIL Cycle time=1s, 100%duty, IIO=0mA, CS10.2V, CS2Vcc-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA CS1=VIH, CS2=VIL, Other inputs=VIH or VIL CSVcc-0.2V, Other inputs=0~Vcc K6T8008C2M-B K6T8008C2M-F Test Conditions Min -1 -1 2.4 Typ Max 1 1 10 12 70 0.4 3 50 80 Unit A A mA mA mA V V mA A
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K6T8008C2M Family
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(see right): CL=100pF+1TTL CL=50pF+1TTL
CMOS SRAM
CL1)
1.Including scope and jig capacitance
AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial product: TA=0 to 70C, Industrial product: TA=-40 to 85C)
Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Read Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5 55ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 70ns Max 70 70 35 25 25 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1Vcc-0.2V1) Vcc=3.0V, CS1Vcc-0.2V1) Min 2.0 0 5 Typ Max 5.5 202) Unit V A ms
See data retention waveform
1. CS1Vcc-0.2V,CS2Vcc-0.2V(CS1 controlled) or CS2Vcc-0.2V(CS2 controlled). 2. Industrial product=30A
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K6T8008C2M Family
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH
OE tOLZ tLZ Data Valid tOHZ
Data out
NOTES (READ CYCLE)
High-Z
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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K6T8008C2M Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4)
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1
Controlled)
tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
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Revision 1.00 February 2000
K6T8008C2M Family
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC Address tAS(3) CS1 tAW CS2 tCW(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4)
CMOS SRAM
WE
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high tWR2 applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
VCC 4.5V tSDR Data Retention Mode tRDR
2.4V VDR CS1VCC - 0.2V
CS1 GND
CS2 controlled
VCC 4.5V CS2 tSDR
Data Retention Mode
tRDR
VDR 0.4V GND CS20.2V
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K6T8008C2M Family
PACKAGE DIMENSIONS
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
CMOS SRAM
Unit: millimeters(inches)
0~8 0.25 ( ) 0.010
#44
#23 0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
10.16 0.400
( 0.50 ) 0.020
#1
#22 1.000.10 0.0390.004 1.20 MAX. 0.047
0.15 0.0
0 + 0.1 5 - 0.0 .0 04 +0 06 - 0.002
18.81 MAX. 0.741 18.410.10 0.7250.004
( 0.805 ) 0.032
0.35 0.10 0.0140.004
0.80 0.0315
0.05 MIN. 0.002
0.10 MAX 0.004
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
( #1 #22 0.25 ) 0.010
0~8
0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
10.16 0.400
( 0.50 ) 0.020
#44
#23 1.000.10 0.0390.004 1.20 MAX. 0.047
0.15 0
0 + 0.1 5 - 0.0 .004 +0 02 .006 - 0.0
18.81 MAX. 0.741 18.41 0.10 0.7250.004
( 0.805 ) 0.032
0.350.10 0.0140.004
0.80 0.0315
0.05 MIN. 0.002
0.10 0.004 MAX
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Revision 1.00 February 2000

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